1. Field of the Invention
The present invention is generally directed to the field of manufacturing integrated circuit devices, and, more particularly, to a method of forming memory devices by performing halogen ion implantation and diffusion processes
2. Description of the Related Art
Manufacturing integrated circuit devices is a very competitive and complex undertaking. Customers frequently demand that such integrated circuit devices exhibit increased performance capabilities as successive generations of products are produced. This is particularly true in the field of manufacturing memory devices, such as flash memory devices.
Flash memory devices are in widespread use in modern electronic devices, e.g., PDAs, cell phones, etc. A typical flash memory device comprises a so-called tunnel oxide layer, a floating gate, an inter-gate or inter-poly layer 26 (e.g., an ONO (oxide-nitride-oxide) stack), and a control gate. Such devices are well known in the art.
In operation, a voltage is applied to the control gate and to the source region of the flash memory device. Such voltage causes electrons to tunnel through the tunnel oxide layer and become trapped in the floating gate. The presence or absence of this trapped charge can be detected and represents a bit of information, i.e., a “1” or a “0”. To delete this charge, a different voltage is applied to the control gate and a drain region of the memory device. During this process, the electrons trapped in the floating gate tunnel back through the tunnel oxide layer, thereby depleting the charge on the floating gate.
Flash memory cells are subjected to thousands of programming and erase operations during normal operations. The effectiveness and speed of such programming and erase cycles can degrade over time, e.g., after a flash memory cell has been subjected to 10,000 or more program and erase cycles. Such degradation may be due, at least in part, to charges being trapped in the so-called tunnel oxide layer of a typical flash memory device.
Flash memory devices may have a well-known NAND configuration in which the memory cells are connected in series. Such NAND architecture employs one or more select gate structures that are used to control access to the memory cells. Typically, the LDD implant regions adjacent the select gate structures and the word line structures in the cell array are formed at the same time using the same implant process. However, such a process flow is undesirable from a performance optimization viewpoint. More specifically, all other things being equal, it would be desirable for the LDD regions in the cell area to be relatively shallow to thereby reduce short channel effects on the cell devices. In contrast, the doped regions for the select gate structure would preferably be relatively deep to reduce adverse effects such as gate induced drain leakage (GIDL).
The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.